sdb dVideoFormatCompiler @A8Ah˨ODY_VTGtamasi_1600x1024_60___1056@M(@> >6> >%NoneA&܀? @M(?Af`0VTG1@Zڐ@[=@Zɻw'@M((0@h@@?0 (@B7~( E E2 Eڊ( E E2 E%(*E*E2*Eڪ*((E(E2(Eڨ>((D(D2(DڨR((D(D2(Fڨf (F(B (B(F((Fڨz (F(B (B(F((fP `f`b`b`"`&060&0.0.@@@@@@@@@@@"0.@@@@@@@@@@@H n f f `f`b`b`"`&060&0.0.@@@@@@@@@@@"0.@@@@@@@@@@@H n f f (f(b (b(f(v(f(fڨ (f(b (b(f((fڨ8 (f(b (b(f((d-(dP((d(d2(dڨj )3=IUrok0(@AchievedFramesPerSecond|AchievedFrequencytActiveLinesPerFrameActivePixelsPerLine BeginTimeCSyncCorrespondingPolarityDACRateMaximumDACRateMinimumDCB_FreqDCDHorizontalBackPorchDCDHorizontalFrontPorchDCDHorizontalSync DCDSupportDCDTotalPixelsPerLineDesiredFrequency<DisplayArchitecture Enable_StereoEndTimeFetchExtraClocks FieldColorFieldCountMaximumFieldEyeFieldLineCountFieldLineOffset FieldLineSkip FieldSwapFieldsPerFrameFormatInfo_DigitalSkewTFormatInfo_DualHeadPFormatInfo_F_0_ActiveLineCount FormatInfo_F_0_V_Active FormatInfo_F_0_V_BackPorch FormatInfo_F_0_V_FrontPorch FormatInfo_F_0_V_Sync FormatInfo_F_0_V_SyncPulse FormatInfo_FieldSequential FormatInfo_FullScreenStereo FormatInfo_H_Active FormatInfo_H_BackPorch FormatInfo_H_FrontPorch FormatInfo_H_Sync FormatInfo_Interlaced FormatInfo_PixelClock FormatInfo_Stereo FormatInfo_UnbalancedSwaps  FormatNameFrameBufferHeightFrameBufferWidthFramePortionIndex FrameTab `FramesPerSecondFullScreenStereo$ GENScanFormat GEN_AMI_REG1@ GEN_AMI_REG2D GEN_AMI_REG5H GEN_AMI_REG6LGEN_Control_mask(GEN_PLL_InputControl8GEN_PLL_Osc_Div<HBlankHorizontalBackPorch(HorizontalFrontPorch0HorizontalSync8HorizontalSync_P$ICS_AchievedFramesPerSecondLICS_AchievedFrequencyD Invert_StereoLineLengthMaximumLineLengthTime@ LineSeqTab~d LineTypeCount MinHBlankMonitorFrameRateMaximumHMonitorFrameRateMinimumPMonitorLineRateMaximumXMonitorLineRateMinimum`MonitorVerticalBlankingMaximumhMonitorVerticalBlankingMinimumpODY_2CHANNEL_FPGA_0`ODY_2CHANNEL_FPGA_1dODY_2CHANNEL_FPGA_2hODY_2CHANNEL_FPGA_3lODY_2CHANNEL_FPGA_4pODY_2CHANNEL_FPGA_5tODY_2CHANNEL_PLL_reg0xODY_2CHANNEL_PLL_reg1|ODY_2CHANNEL_PLL_reg2ODY_2CHANNEL_PLL_reg3ODY_2CHANNEL_PLL_reg4ODY_2CHANNEL_PLL_reg5ODY_2CHANNEL_PLL_reg6ODY_2CHANNEL_PLL_reg7ODY_2CHANNEL_RAMDAC_ctrlXODY_2CHANNEL_TMDS_ctrl\ODY_AMI_PLL_0x0TODY_AMI_PLL_0x1XODY_AMI_PLL_0x2\ODY_AMI_PLL_0x3`ODY_AMI_PLL_0x4dODY_AMI_PLL_0x5hODY_AMI_PLL_0x6lODY_AMI_PLL_0x7p ODY_DAC_CntrlODY_DCBClockSpeedODY_DDCClockSpeed ODY_DP_Cntrl ODY_GENLOCK ODY_GEN_BP_CLAMPODY_GEN_CONTROLODY_GEN_hHMASK ODY_GEN_hPFDODY_GEN_hPFD_HIODY_GEN_hPFD_LO ODY_GEN_hPSDODY_GEN_lHMASK ODY_GEN_lPFDODY_GEN_lPFD_HIODY_GEN_lPFD_LO ODY_GEN_lPSDODY_I2CClockSpeedODY_Multibuzz_SM_CntrlODY_PLL_DPAControl0ODY_PLL_DPAOffset,ODY_PLL_FdBkDiv0$ODY_PLL_FdBkDiv1(ODY_PLL_InputControlODY_PLL_LoopControl ODY_PLL_Osc_Div8ODY_PLL_OutputEnables4 ODY_SM_CntrlODY_VTG_ChanEnODY_VTG_ControlODY_VTG_InitStateOptionHardware|PFDVerticalPhaseBiasx RS343A_Levels ScreenHeightSignalInitialStateValidSignalInitialStateValueStateRepetitionMaximum SwapsPerFrameSystemFrameRateMaximumSystemFrameRateMinimumSystemLineRateMaximumSystemLineRateMinimumSystemVideoClockRateMaximumSystemVideoClockRateMinimumTTL_SyncTotalLinesPerFrameTotalPixelsPerLineTotalSignalCountTransitionDirectionHighTransitionDirectionLowTransitionDirectionSupportVFCMajorVersionVFCMinorVersion VSyncLinesVTGHardwareNameVTG_ChanDisable_mask4VTG_ChanEn_mask0VTG_Control_mask, Verif_FmtVerticalRetraceRateVerticalStateCount VfoVersionVideoClockRatioVideoClockRatioDenominatorVideoClockRatioNumeratoryydebug